[ACCEPTED]-Why is Verilog not considered a programming language?-verilog

Verilog, just like VHDL, is meant to describe 24 hardware. Instead, programming languages 23 such as C or C++ provide a high level description 22 of software programs, that is, a series 21 of instructions that a microprocessor executes.

In 20 practice, Verilog and VHDL do not offer 19 the same features as programming languages, even 18 though they look very much alike. For instance, a 17 for loop in C/C++ describes the sequential execution 16 of a given snippet of code; instead, a for ... generate loop 15 in Verilog/VHDL describes multiple parallel instances 14 of a same hardware building block (say, a 13 AND logic gate). To be precise, there also 12 exists a plain for loop in Verilog, but again, it 11 has to be "synthesizable", that is, the 10 compiler must be able to generate logic 9 that fits the description.

Typically, a 8 beginner in Verilog/VHDL will be tempted 7 to "translate" a given function/algorithm 6 from a C/C++ type of pseudocode directly 5 to Verilog/VHDL: surprisingly, it might 4 sometimes work, but it always lead to dramatically 3 poor design. One must really be aware of 2 these differences in order to become a good 1 Verilog/VHDL programmer.

Verilog is a hardware definition language. Programming 3 languages are generally understood to be 2 languages for telling existing hardware 1 what to do, not for reconfiguring said hardware.

It is a programming language, not to program 4 software, but to describe hardware design 3 - but the output is not necessarily an "application" as 2 we understand it.

The language has a formal 1 syntax.

I don't know anything about Verilog but 53 just did a quick googling and the wiki pages 52 seem to do a pretty good job of explaining 51 the differences in concept that your teacher 50 seemed to be eluding to. As some of the 49 other posters here wrote I don't know that 48 I would dismiss this as not a programming 47 language, I think there's a high tendency 46 for programmers to believe if it isn't somehow 45 application programming or assembly programming 44 then it's not really programming, but in 43 short that's BS. Everything above machine 42 code is basically the same to me, if it's 41 a file I give to a computer and it tells 40 the computer how to do something it's programming 39 the computer (I guess the problem is drawing 38 a line between users and developers, we 37 like to feel special). Unless we plan to 36 roll back to punch-cards sometime soon, I 35 think anything that has a C like syntax 34 or allows you to describe in a syntactically 33 strict (well defined) way and modifies the 32 behavior of the computer (what it outputs 31 for a given input) then you've done some 30 programming in one sense or another.

http://dictionary.reference.com/browse/programming

From 29 the wiki page:

http://en.wikipedia.org/wiki/Dataflow_language

Dataflow programming focuses 28 on how things connect, unlike imperative 27 programming, which focuses on how things 26 happen. In imperative programming a program 25 is modeled as a series of operations (thing 24 that "happen"), the flow of data 23 between these operations is of secondary 22 concern to the behavior of the operations 21 themselves. However, dataflow programming 20 models programs as a series of (sometimes 19 interdependent) connections, with the operations 18 between these connections being of secondary 17 importance.

(I think the key here is the 16 qualifiers of the type of programming not 15 that one is a "programming language" and 14 the other is a "design language", from 13 what I understand they're both programming 12 languages they just have distinct purposes 11 and implementations). When I think of design 10 I basically think of this: http://dictionary.reference.com/browse/design and that is 9 not a program although a program may utilize 8 designs (and probably should, generally 7 referred to as design patterns, but not 6 what you're doing)

Linked in from: http://en.wikipedia.org/wiki/Verilog

To your 5 teachers point this language would likely 4 be used to solve different problems from 3 your every day Java/C program, and via a 2 different means, however to say it is not 1 a program seems wrong.

Because it is an HDL, so it is to define 9 hardware, and anything done in verilog (not 8 really anything, but synthesizable things) will 7 be synthesized into actual hardware. So 6 you can't just use programming features 5 like class and OOPS concept because it can't 4 create any hardware.

But in C, everything 3 will be converted into executable hex file, which 2 will be loaded in your ram while executing 1 the program.

Another basic difference is everything in hardware is concurrent, so if you have written a=b+1 and c=d+1 in verilog, then in the synthesized hardware, both modules will work simaltaneously. But in C everything is sequential, so in same C program actually both instruction will be loaded one by one in your processor.

Verilog contains features to describe logical 7 netlists(RTL) and features to facilitate 6 simulation of them. Describing an RTL description 5 as a program may convey that one who describes 4 it as such does not throughly understand 3 logic design or synthesis. Describing a 2 testbench stimulus as a program would be 1 appropriate.

verilog/vhdl is used to create and design 3 specific application system on the chip 2 which embedded into electronic devices.

c/c++ used 1 design softwares on the computer

I am going to tackle this question in a 9 different way. What is a purpose of a programming 8 language? Can the output of a program affect 7 real world and your goals and expectation? If 6 yes then ofcourse verilog is a programming 5 language. Console.log has as much meaning 4 as what it translates to in real world eg. console.log("you 3 have a million unit") has no fiat without 2 authority. So verilog is a programming language 1 in certain sense.