[ACCEPTED]-How do interrupts work on the Intel 8080?-intel-8080

Accepted answer
Score: 23

The 8080 has an Interrupt line (pin 14). All 69 peripherals are wired to this pin, usually 68 in a "wire-OR" configuration (meaning interrupt 67 request outputs are open-collector and the 66 interrupt pin is pulled high with a resistor). Internally, the 65 processor has an Interrupt Enable bit. Two 64 instructions, EI and DI, set and clear this 63 bit. The entire interrupt system is thus 62 turned on or off, individual interrupts 61 cannot be masked on the "bare" 8080. When 60 a device issues an interrupt, the processor 59 responds with an "Interrupt Acknowledge" (~INTA) signal. This 58 signal has the same timing as the "Memory 57 Read" (~MEMR) signal and it is intended 56 to trigger the peripheral device to place 55 a "Restart" instruction on the data bus. The 54 Interrupt Acknowledge signal is basically 53 an instruction fetch cycle, it occurs only 52 in response to an interrupt.

There are eight 51 Restart instructions, RST 0 - RST 7. RST 50 7 is opcode "0xFF". The Restart instructions 49 cause the processor to push the program 48 counter on the stack and commence execution 47 at a restart vector location. RST 0 vectors 46 to 0x0000, RST 1 vectors to 0x0008, RST 45 2 vectors to 0x0010 and so on. Restart 44 7 vectors to 0x0038. These vector addresses 43 are intended to contain executable code, generally 42 a jump instruction to an interrupt service 41 routine. The Interrupt Service Routine 40 will stack all of the registers it uses, perform 39 the necessary I/O functions, unstack all 38 the registers and return to the main program 37 via the same return instruction that ends 36 subroutines (RET, opcode 0xC9).

Restart instructions 35 are actual opcodes, meaning they will do 34 the same thing if they are fetched from 33 memory during program execution. It was 32 convenient to use Restart 7 as "warm restart" for 31 a keyboard monitor / debugger program because 30 early EPROMs generally contained 0xFF in 29 each blank location. If you were executing 28 blank EPROM, that meant something had gone 27 awry and you probably wanted to go back 26 to the monitor anyway.

Note that RST 0 vectors 25 to the same memory location as RESET, both 24 start executing at 0x0000. But RST 0 leaves 23 a return address on the stack. In a way, RESET 22 can be thought of as the only non-maskable 21 interrupt the 8080 had.

An interrupt signal 20 will also clear the Interrupt bit so an 19 Interrupt Service Routine will need to execute 18 an EI instruction, generally immediately 17 before the RET. Otherwise, the system will 16 respond to one and only one interrupt event.

CP/M 15 reserved the first 256 bytes of memory for 14 system use -- and that interrupt vector 13 map used the first 64 bytes (8 bytes per 12 Restart instruction). On CP/M systems, RAM 11 started at 0x0000 and any ROM lived at the 10 top end of memory. These systems used some 9 form of clever bank switching to switch 8 in an EPROM or something immediately after 7 a RESET to provide a JUMP instruction to 6 the system ROM so it could begin the boot 5 sequence. Systems that had ROM at the low 4 end of the memory map programmed JUMP instructions 3 to vectors located in RAM into the first 2 64 bytes. These systems had to initialize 1 those RAM vectors at startup.

Score: 1

The 8080 was dependent on external hardware 4 to control its handling of interrupts, so 3 it is impossible to generalize. Look for 2 information on the Intel 8214 or 8259 interrupt 1 controllers.

Score: 1

I finally find it!

I create a variable called 5 bus where interruption opcode goes. Then, I 4 called a function to handle the interruption:

void i8080::interruption()
    // only for RST
    cycles -= cycles_table[bus];
    INT = false;

INT 3 is true when needs an interruption. EI and 2 DI instructions handle INTE.

When INT and 1 INTE is true interruption is executed.

Score: 0

Function pointers to the interrupt handlers 14 are stored in the low memory. Some 32 or 13 so of the first addresses are hardware interrupts: hardware 12 triggered.

The next 32 or so address are 11 user-triggerable, these are called software 10 interrupts. They are triggered by an INT instruction.

The 9 parameter to INT is the software interrupt 8 vector number, which will be the interrupt called.

You 7 will need to use the IRET instruction to return 6 from interrupts.

It's likely you should also 5 disable interrupts as the first thing you 4 do when entering an interrupt.

For further 3 detail, you should refer to the documentation 2 for your specific processor model, it tends 1 to vary widely.

Score: 0

An interrupt is a way of interrupting the 39 cpu with a notification to handle something 38 else, I am not certain of the Intel 8080 37 chip, but from my experience, the best way 36 to describe an interrupt is this:

The CS:IP (Code 35 Segment:Instruction Pointer) is on this 34 instruction at memory address 0x0000:0020, as 33 an example for the sake of explaining it 32 using the Intel 8086 instructions, the assembler is gibberish and has no real meaning...the instructions are imaginative

0x0000:001C   MOV AH, 07
0x0000:001D   CMP AH, 0
0x0000:001E   JNZ 0x0020
0x0000:001F   MOV BX, 20
0x0000:0020   MOV CH, 10   ; CS:IP is pointing here
0x0000:0021   INT 0x15

When 31 the CS:IP points to the next line and an 30 INTerrupt 15 hexadecimal is issued, this is 29 what happens, the CPU pushes the registers 28 and flags onto the stack and then execute 27 code at 0x1000:0100, which services the 26 INT 15 as an example

0x1000:0100   PUSH AX
0x1000:0101   PUSH BX
0x1000:0102   PUSH CX
0x1000:0103   PUSH DX
0x1000:0104   PUSHF
0x1000:0105   MOV ES, CS
0x1000:0106   INC AX
0x1000:0107   ....
0x1000:014B   IRET

Then when the CS:IP 25 hits on the instruction 0x1000:014B, an 24 IRET (Interrupt RETurn), which pops off ALL 23 registers and restore the state, is issued 22 and when it gets executed the CPU's CS:IP 21 points back to here, after the instruction 20 at 0x0000:0021.

0x0000:0022   CMP AX, 0
0x0000:0023   ....

How the CPU knows where to 19 jump to a particular offset is based on 18 the Interrupt Vector table, this interrupt 17 vector table is set by the BIOS at a particular 16 location in the BIOS, it would look like 15 this:

---    --------------------------------------
0      0x3000
1      0x2000
..      ....

That table is stored in the BIOS and 14 when the INT 15 is executed, the BIOS, will 13 reroute the CS:IP to the location in the 12 BIOS to execute the service code that handles 11 the interrupt.

Back in the old days, under 10 Turbo C, there was a means to override the 9 interrupt vector table routines with your 8 own interrupt handling functions using the 7 functions setvect and getvect in which the actual interrupt 6 handlers were re-routed to your own code.

I 5 hope I have explained it well enough, ok, it 4 is not Intel 8080, but that is my understanding, and 3 would be sure the concept is the same for 2 that chip as the Intel x86 family of chips 1 came from that.

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